Virtual Nanofabrication

A collection of collaborative research projects between CCNI and IBM, the Virtual Nanofab envisions a suite of computational tools in which micro- and nano-electronic devices can be designed, tested, and produced completely in silico.

Participating projects:

First-principles nano-electronic CMOS modeling

Principal Investigator: Saroj Nayak

Employing first-principles calculations, as well as iteratively reconciling those calculations to continuum analysis such as Poisson-based field models, we are able to analyze nano-electronic systems such as single electron transitors, functionalized carbon nanotubes, and graphene-based devices.

Strain-induced defect production in strained semiconductors

Principal Investigator: Catalin Picu

By inducing strain in silicon and other semiconductors, carrier mobility can be increased. However, such strains can give rise to dislocations and other defects. We are able to characterize how and where such systems can produce device-killing defects

Figure 1: (left) Continuum FEM models are employed on larger scales, automatically creating (right) atomistic sub-problems for detailed analysis in areas of high strain.

Super-resolution holographic lithography

Principal Investigator: Assad Oberai

By using electromagnetic interference patterns rather than projective techniques, lithographic resolution can be more than doubled for a given wavelength. However, the biasing corrections made for OPC no longer apply, and new techniques are needed to design and analyze holographic masks. We adjoint solutions to Maxwell's equations to accelerate the inner loop of a mask optimizer, allowing us to quickly create highly effective holographic masks giving near optimal dose contrast.

Figure 2: (top) Schematic of construction process of a holographic mask. (bottom) Dose seen by photoresist as holographic mask parameters are optimized, starting at left and proceeding to optimal mask on right.

Plasma etch modeling

Principal Investigator: Max Bloomfield

Reactive ion etching (RIE) is the industry standard method for transferring patterns to the wafer. We use physically based models of transport and reaction to model the etching process on the sub-micron feature scale, driving these simulations from equipment-scale simulations. These multiscale analyses cross six orders of magnitude in size scale and seven orders of magnitude in time scale.

Figure 3: Schematic of ion and neutral species arriving from a plasma, reaching the substrate through an opening in the photomask. The ions move directionally, in response to the electric field, and the neutral species move with the normal Maxwellian distribution.

Figure 4: An L-shaped trench etched through a mask using a reactive-ion etch. Note the combination of anisotropic etch with an isotropic component, giving rise to the mask 'undercut'.

Advanced mesh tools for nano-electronic design

Principal Investigator: Mark Shephard

Device analysis is computationally intensive due to the complicated geometric structures assocaiated with micro- and nan-electronic devices. By using advanced meshing techniques, such as on-the-fly adaptation and local refinement, essential analyses of even highly complicated non-planar devices can be accelerated and computational resources stretched further.

Figure 5: High-quality, locally refined meshes can be constructed for (left) complex BEOL structures and (right) front-end devices. Such meshes put degrees of freedom where they are really needed while creating more tractable numerical systems for solvers.