A collection of collaborative research projects between CCNI and IBM, the Virtual Nanofab envisions a suite of computational tools in which micro- and nano-electronic devices can be designed, tested, and produced completely in silico.
- First-principles nano-electronic CMOS modeling
- Strain-induced defect production in strained semiconductors
- Super-resolution holographic lithography
- Plasma etch modeling
- Advanced mesh tools for nano-electronic design
Principal Investigator: Saroj Nayak
Employing first-principles calculations, as well as iteratively reconciling those calculations to continuum analysis such as Poisson-based field models, we are able to analyze nano-electronic systems such as single electron transitors, functionalized carbon nanotubes, and graphene-based devices.
Principal Investigator: Catalin Picu
By inducing strain in silicon and other semiconductors, carrier mobility can be increased. However, such strains can give rise to dislocations and other defects. We are able to characterize how and where such systems can produce device-killing defects
Principal Investigator: Assad Oberai
By using electromagnetic interference patterns rather than projective techniques, lithographic resolution can be more than doubled for a given wavelength. However, the biasing corrections made for OPC no longer apply, and new techniques are needed to design and analyze holographic masks. We adjoint solutions to Maxwell's equations to accelerate the inner loop of a mask optimizer, allowing us to quickly create highly effective holographic masks giving near optimal dose contrast.
Principal Investigator: Max Bloomfield
Reactive ion etching (RIE) is the industry standard method for transferring patterns to the wafer. We use physically based models of transport and reaction to model the etching process on the sub-micron feature scale, driving these simulations from equipment-scale simulations. These multiscale analyses cross six orders of magnitude in size scale and seven orders of magnitude in time scale.
Principal Investigator: Mark Shephard
Device analysis is computationally intensive due to the complicated geometric structures assocaiated with micro- and nan-electronic devices. By using advanced meshing techniques, such as on-the-fly adaptation and local refinement, essential analyses of even highly complicated non-planar devices can be accelerated and computational resources stretched further.